Over the recent years a growing interest has been seen in the area of highly integrated semiconductor device that can be used for power management and signal amplification.
U.S. Pat. No. 5,126,806 describes a lateral insulated gate bipolar transistor (IGBT), Ref. 1, which is particularly well suited for high power switching applications. Disclosed is an enhancement-IGFET device having its source and drain electrodes connected to the base and emitter, respectively, of a lateral bipolar transistor. When an appropriate gate input voltage, here in the form of a positive charge, is applied to the IGFET, the channel conducts, thus biasing the bipolar transistor into conduction. The applied charge on the gate electrode can be used to control a large current through the bipolar device, which is of particular interest in power applications. Safe switching operation at high voltages however requires a very wide base and a low gain in the bipolar transistor. Various forms of said devices have been integrated in modern CMOS processes as described by Bakeroot et. al. in IEEE EDL-28, pp. 416-418, 2007, Ref. 2. Relevant in this context is also a report by E. Kho Ching Tee entitled “A review of techniques used in Lateral Insulated Gate Bipolar Transistor (LIGBT)” in Journal of Electrical and Electronics Engineering, vol. 3, pp. 35-52, 2012, Ref. 3. While this type of device is potentially quite useful for various forms of power switching, with its requirements of high voltage capability and low internal gain, it is disadvantageous for a device incorporated in a low voltage highly integrated circuit intended for power management and signal amplification.
FIG. 1A shows one example of prior art in the form of a lateral insulated gate bipolar transistor device (LIGBT) such as described in U.S. Pat. No. 5,126,806 by Sakurai et. al. mentioned above. The integrated device 30 is constructed in a low-doped n-type layer 35 containing a p-type doped layer 50 with a higher impurity concentration than that of the n-type layer and a p+ layer 70 with an impurity concentration exceeding that of the p-type doped layer 50. In the p-doped layer 50 is provided an n+-layer 60 with an impurity concentration that is higher than that of the p-type layer 50. The p-doped layer 50 and the n+-layer 60 are electrically short-circuited by an emitter electrode 55. A collector electrode 65 forms an ohmic contact to the p+-layer 70. An insulating film serves as gate dielectric 40 and separates the gate electrode 45 from the substrate.
When a positive potential is applied to the gate electrode 45, the conductivity of a surface portion of the p-layer 50 under the gate dielectric 40 is inverted to form an n-type channel. Electrons from the n+-layer 60 can then pass through the channel from the n-layer 35 to the p+-layer 70 from which positive holes are injected. Thereby the n-layer 35, having a high resistivity, is conductivity-modulated to provide a low resistance path between the anode (C) and cathode (E) in FIG. 1A. A low on-resistance and excellent forward blocking characteristic can thus be realized, which is quite useful for various forms of power switching.
Numerous modifications of the above described embodiment, with emphasis on improved switching performance, exist, some of which are covered in a report entitled “A review of techniques used in Lateral Insulated Gate Bipolar Transistor (LIGBT)” by E. Kho Ching Tee published in Journal of Electrical and Electronics Engineering, vol. 3, pp. 35-52, 2012.
FIG. 1B, is an equivalent electrical circuit diagram for the device in FIG. 1A. Shown are the three terminals, C, E and G. The device also utilizes an external back-side substrate electrode. The n-type IGFET has its source and body terminals strapped together at (E) and these are, in turn, connected to the collector layer (C) of the lateral bipolar pnp-transistor over the body resistance, R1. Shown is also how the base terminal of the lateral pnp-transistor is connected to the drain of the IGFET over a variable resistance, R2, the latter mirroring the conductivity modulation.
A vertical parasitic npn-transistor that has its base connected to the collector of the lateral pnp-transistor is included in FIG. 1B to illustrate that the LIGBT contains a thyristor-like structure. Once this thyristor causes latch-up, the LIGBT device can no longer be controlled by the gate potential. The condition for latch-up is: αnpn+αpnp≧1, where αnpn and αpnp are the common-base current gains of the parasitic npn transistor and pnp transistor, respectively. To reduce the risk for latch-up it is essential to lower the current gain α in both transistors. Since the pnp transistor carries the on-state voltage drop, the gain of the npn-transistor has to be suppressed by, e.g., increasing the base doping below the emitter layer (lowering the base resistance).